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TM58P20
1.Feature
ROM: 2K x 14 bits RAM: 96 x 8 bits STACK: 4 Levels I/O ports: 20 I/O PAD Timer/counter: 8bits x1 (TMR0) Prescaler: 8 Bits Two IRQ sources: Internal IRQ: (TMR0) External IRQ: (PA0) Watchdog Timer: On chip WDT is based on internal RC oscillator. The shortest period is 20mS; user can extend the WDT overflow period to 2.6S by using prescaler. Power-On Reset & Power-Down Reset Reset Timer: 20 mS (5V) Four external Oscillate modes: RC,LP Crystal,NT Crystal and HS Crystal. Two operation modes: General mode, and Advanced mode Operation Voltage: 2.2Va 5.5V Instruction set: 79 Wake-up: Watchdog timer overflow, Port A (PA3~ PA0) Reset vector: 7FFH IRQ vector: 7FEH Low voltage reset: voltage shortage will result in reset
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2. Pin Definition & Pad Assignment
RTCC VDD NC VSS NC PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RESETB/VPP OSC1 OSC2 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5
Package Types of 28Pin: DIP, SOP. RESETB/VPP RTCC VDD VSS PA0 PA1 PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OSC1 OSC2 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4
Package Types of 20Pin: DIP, SOP.
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PIN description Pin name RTCC PA0 PA3-1 PB7-0 PC7-0 RESETB/VPP OSC1 OSC2 VDD VSS I/O I I/O I/O I/O I/O I I O P P Description External clock input to TMR0 counter I/O port & External IRQ input & wake-up input I/O port & wake-up (input mode) I/O port I/O port System reset signal & VPP (High voltage) input 1 Low voltage: reset mode 2 High voltage: programming mode Oscillator input Oscillator output Power input Ground input I: Input; O: Output; I/O: Bi-direction; P: Power
3. Control Register
Name CONFIG (Instruction) SELECT IAR TMR0 PC STATUS BSR I/O PortA I/O PortB I/O PortC WAKE_UP IRQM IRQF Addr Bit 7 Bit 6 LV1 Bit 5 LV0 Bit 4 Bit 3 Bit 2 WDTE PS2 A2 D2 D2 Z D2 PA2 PB2 PC2 PUH2 EXINTM EXINTF Bit 1 Bit 0
TYPE CPT
FOSC1 FOSC0 PS1 A1 D1 D1 DC D1 PA1 PB1 PC1 PUH1 PS0 A0 D0 D0 C D0 PA0 PB0 PC0 PUH0 TMR0M TMR0F
SUR0 EDGE0 PSA $00 $01 $02 $03 $04 $05 $06 $07 $20 $21 $22 PB7 PC7 INTM PB6 PC6 PB5 PB5 EIS PB4 PC4 D7 A7 D7 D7 A6 D6 D6 SA1 D6 A5 D5 D5 SA0 D5 A4 D4 D4
TO D4
A3 D3 D3
PD D3
PA3 PB3 PC3 PUH3
WDTS WUE
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TM58P20
4. System Block Diagram
Interrupt Controller
Instruction Register
EPROM
PC7:PC0 PB7:PB0 PA3~0 PB7~0 PC7~0 I/O Port PA3:PA0 Instruction Decoder
Program Counter
4 Level stacks Data Bus
TMR0
Select Register
Status
Acc
BSR
WDT/TMR0 Prescaler
ALU and Control Unit
RAM
Watch Dog Timer
Oscillator & Low voltage detector Sleep
Configuration
Word
RTCC
OSC1
OSC2
RESETB/VPP
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5. Memory Map
TM58P20 memory is organized into program memory and data memory. 5.1 Program memory TM58P20 provides 2 program memory maps, general mode and advanced mode. User can select different mode by setting configuration word. In general mode, there are only 512 words of the same page that can be directly addressed. Extra program memory can be addressed by setting bit 6~5 of status register. The sequence of instructions is controlled via the program counter (PC), which automatically increases 1. However, the sequence can be changed by "skip", "call" and "goto" instructions or by moving data to the PC. In advanced mode, TM58P20 allow directly goto any address in 2K memories without limited by page size. In addition, "lcall" and "lgoto" instructions are employed to provide flexible addressing mode. TM58P20 has an 11-bits program counter capable of accessing 2K spaces. If accessing address has over 2K, then the address will map to physical 2K memories, i.e. 2K+M will be mapped to M. A NOP at the reset vector location will cause a restart at address 000h. A simple map to induce illustrate ROM organization is shown in figures 5-1. General Mode
000H
Advance Mode
000H ... ... ...
Page 0
1FFH 200H
Page 1
3FFH 400H
Program
... ... 7FDH 7FEH
Page 2
5FFH 600H
IRQ vector
7FFH
Page 3
7FEH 7FFH
Reset vector
Reset vector Figure 5-1 The ROM Organization
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TM58P20 only provide IRQ function in advanced mode. In this mode, the address 7FEH is reserved for IRQ vector. User can operate advanced mode by setting configuration word. The configuration word is located 800H that contains OSC selection, WDT enable, code protection, operate type selection and low voltage reset selection. Bit Symbol Bit1 0 0 1 1 2 WDTE Bit0 0 1 0 1 Description OSC Type LP (low speed) NT(Normal speed) HS (high speed) RC Resonance Frequency 32~200K hz 200K~10M hz 10~20M hz 32K ~ 6M hz
1~0 FOSC1~FOSC0
3
CPT
4
TYPE
WDTE: Watchdog enable/disable control 1: WDT enable 0: WDT disable CPT: Code Protection bit 1: OFF 0: ON TYPE: Select operating mode 1: Advanced mode 0: General mode LV1 LV0 Detect voltage 1 1 1 0 0 Don't use Don't use 2V 4V 0 1 0
6~5
LV1~LV0
Figure 5-2 The Configuration Word
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5.2 Data memory Data memory is composed of special function registers and general-purpose ram. The size of data memory is not stationary, it depends on bit 4 of configuration word (general or advanced mode). 5.2.1 General Mode In general mode, TM58P20 has 72 general-purpose registers that accessed by using a bank select scheme. The special function registers include the program counter (PC), the timer (TMR0) register, the status register, the bank select register, and the I/O port registers. Furthermore, TM58P20 has 3 auxiliary registers that include indirect addressing register (IAR), the select register (Select) and the I/O direction register (IODIR). The register map of general mode is shown in figure 5-3. Bank0 IAR TMR0 PC STATUS BSR PORTA PORTB PORTC General Purpose Register General Purpose General Purpose General Purpose General Purpose Register Register Register Register 10-1F 30-3F 50-5F 70-7F Bank1 Bank2 Bank3
00h 01h 02h 03h 04h 05h 06h 07h 08h~0fh
Map back to address in Bank0
8+16*4=72
Figure 5-3 The Register Map of General Mode
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A. The IAR (indirect addressing register) is not a physical register and is used to assist BSR with indirect addressing. Any instruction attempts to access IAR actually mapping to another address that is pointed by BSR. Since IAR is not a material circuit, user reads IAR itself (BSR=00H) will always return 00h at data bus. Writing to IAR itself will like NOP. B. Select register is used to control WDT and TMR0. It has not assigned a specific address in data memory and can only set control bits by select instruction, i.e. it is write-only register. The context of accumulator will be sent to the select register by executing the select instruction. If select register has never set by program, its default value is 3FH. We drew Figure 5-4 to explain how to set select register.
Description PS2 PS1 PS0 TMR0 rate WDT rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 2~0 PS2~PS0 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 PSA: Prescaler assignment bit 3 PSA 1: Prescaler assigned to WDT 0: Prescaler assigned to TMR0 EDGE0: TMR0 source signal edge control bit 1:increment when H/ L transition on external clock 4 EDGE0 0:increment when L/ H transition on external clock SUR0: TMR0 clock source bit 5 SUR0 1: External clock input 0: (Internal clock)/4 or internal instruction cycle Figure 5-4 Select Register
Bit
Symbol
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C. The I/O Direction control register is similar to the Select register that is write-only register. To set an I/O port pin as input, the corresponding direction control bit must be high. Similarly, the zero represents output. Any direction control bit can be programmed individually as input or output by using "IODIR" instruction. If the register is not programmed, than all I/O ports always keep input mode. PC (program counter) is 11-bit wide binary counter and increases itself for every instruction cycle, except the following instructions. 1. "call", "goto", "lgoto" and "lcall": the label will move to PC 2. "retla", "reti" and "ret": the top value of stack will pop to PC Incrementing PC when it changes to the next higher page. It should be noted that the page select bits in the status register would not be changed synchronously. The following GOTO, CALL, or MOVAM 02H will return to the previous page, unless the page select bits have been updated in program. In order to reduce the complexity of programming, TM58P20 provides 2 instructions to facilitate subroutine call and branch handling which are LCALL and LGOTO. LCALL and LGOTO can address to anywhere in the ROM, but the page select bits are unnecessary. The attached operands of CALL and GOTO are 8-bit and 9-bit respectively, and so need extra bits (page select bits) to address whole memory. However, LCALL and LGOTO have 11bit wide operands that are easy to address the total ROM space. TMR0 is 8-bit wide binary counter/timer. This register increases by an external signal edge applied to RTCC pin, or by internal instruction cycle. It has the following features. A. Readable and writeable B. Synchronize with 2 internal clocks C. Can use programmable prescaler by setting select register The other details will be described in follow-up chapter. Status register contains page select bits, time out bit, power down bit and the status of ALU. Please note that TO and PD are controlled by hardware and unchangeable by program.
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Bit Symbol Description Carry and Borrow bit ADD instruction SUB instruction 1: a carry occurred from the 1: no borrow (Note1) MSB 0:a borrow occurred from the MSB 0: no carry Nibble Carry and Nibble Borrow bit ADD instruction SUB instruction 1: a carry from the low nibble 1: no borrow bits of the result occurred 0: a borrow from the low nibble bits 0: no carry of the result occurred Zero bit: 1: the result of a logic operation is zero 0: the result of a logic operation is not zero Power down flag bit: (Note2) 1: after power-on or by the CLRWDT instruction 0: execute SLEEP instruction Time out flag bit: 1: after power-on or by the CLRWDT or SLEEP instruction 0: Occur WDT time-overflow SA1 SA2 Page Location 0 0 1 1 0 1 0 1 Page 0 (000H~1FFH) Page 1 (200H~3FFH) Page 2 (400H~5FFH) Page 3 (600H~7FFH) Figure 5-5 Status Register Note1: A SUB instruction is executed by adding the 2's complement of the subtrahend, so C = 1 represents positive result. The Figure 5-5-1 show the relation between C-bit and borrow.
0
C
1
DC
2
Z
3
PD
4
TO
6~5 SA1~SA0
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B0H 50H 50H B0H
C B7 B6 B5 B4 B3 B2 B1 B0 I x 10110000 10110000 101100000 I x
C B7 B6 B5 B4 B3 B2 B1 B0 01010000 01010000 010100000
Figure 5-5-1 Note2: The TO and PD bits are active low that can be used to determine different causes of reset. The Figure 5-5-2 illustrates the value of TO and PD after the relative reset events.
TO 0 0 1 1 Unchanged
PD 0 1 0 1 Unchanged
Reset Event WDT time out from sleep mode WDT time out from normal mode Input a "low" at RESETB from sleep mode Power on reset Input a "low" at RESETB from normal mode Figure 5-5-2
BSR (bank select register) is associated with IAR to indirectly access the data memory. The direct addressing must rely on BSR to access bank1 ~ bank3, because there are only 5-bit wide address operands in general mode. The bit 6~5 of BSR are used to select the specifiable memory bank. These address regions 20H~2FH, 40H~4FH and 60H~6FH are not accessible, these address will be mapped to 00H~0FH (Bank0). The addressing map is shown in Figure 5-6.
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Direct addressing mode BSR 6 5 I Operand 4 0 Indirect addressing BSR 654 0
00
0F 10 Select location 1F Select bank Bank0 00
20~2F, 40~4F and 60~6F are unimplemented, these locations will mapping to 00~0F 30 50 70 Select location 3F Bank1 01 5F Bank2 10 7F Bank3 11 Select bank
Figure 5-6 The Direct and Indirect Addressing Map Port A~C are programmable I/O ports. Please note that read I/O instruction always read the I/O pin even though the pin is output mode. On reset, all I/O pins were set as input mode until IODIR has been changed.
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5.2.2 The advanced mode In advanced mode, we provide IRQ, convenient wake up functions and flexible addressing mode. In addition to extend data memory, we increase 3 extra registers to support IRQ and wake_up. This section will introduce these increased control registers and characteristics. The data memory map of advanced mode and the addressing map are shown in figure 5-7 and figure 5-8. Advanced mode ( Type=1 ) 00~1F 00h IAR 01h 02h 03h 04h 05h 06h 07h TMR0 PC STATUS BSR PORTA PORTB PORTC General Purpose General Purpose General Purpose General Purpose Register Register Register Register 08-0F 28-2F 48-4F 68-6F General Purpose General Purpose General Purpose General Purpose Register Register Register Register 10-1F 30-3F 50-5F 70-7F Unimplemented
20~3F WAKE_UP IRQM IRQF
41~5F
60~7F
Unimplemented
8*4+16*4=96
Figure 5-7 The Data Memory Map of Advanced Mode
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Direct addressing mode Operand 6 0 00 20 21 22 6 Unimplemented Indirect addressing BSR
0
u
07 08 28 48 68
Location select 1F 3F 5F 7F
Select location
Figure 5-8 The Direct and Indirect Addressing Map
In advanced mode, we locate the increased 24 general-purpose registers on 28~2F, 48~4F and 68~6F which are shadow regions in Fig 5-7. The IRQ and the wake_up control registers (WAKE_UP, IRQM and IRQF) are assigned to 20, 21 and 22, respectively. In general mode, BSR<6,5> are the bank select bits and used to select the bank (00=bank0, 01=bank1, 10=bank2, 11=bank3). The lower 16 bytes of bank1, 2, and 3 are mapped to bank0. In advanced mode,TM58P20 allows 7-bit wide operand to access ram, operand<6:0> can address 00~7F directly. It doesn't need bank select bits, and reduces the complexity of programming The wake up control register (WAKE_UP) is used to set watchdog enable and distinguish between external wake-up signal and IRQ. On reset, all bits are defined as `0' that can be programming by software. The scheme of WAKE_UP register is shown in Fig 5-9.
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TM58P20
Bit Symbol Description Watch Dog Timer Software Control bit: TM58P20 has 2 WDT control bits (WDTE and WDTS), WDTE is set in configuration word by hardware and WDTS is set in control register by software. If WDTS is valid only if WDTE has been set, i.e. WDTE has higher priority than WDTS. 1: enable 0: disable
7
WDTS
6
WUE
Wake Up Enable bit: 0: don't support external wake-up 1: enable external wake-up function External Interrupt Select: 1: set PA0 as an external IRQ pin (Note3) 0: set PA0 as a bi-directional I/O pin Unimplemented
5 4
EIS ----
Pull High Port A bit3 ~1: 0: disable external wake up 3~1 PUH3~PUH1 1: if (WUE) & (PUHN) & (input a falling edge signal at PAN) then wake up chip from sleep. N can be 3, 2 or 1, but it must keep consistent. Pull High Port A bit0: 0: disable external wake up and external IRQ 1: if (WUE) & (PUH0) & (input a falling edge signal at PA0) then wake up chip from sleep. 0 PUH0 Or if (EIS) & (PUH0) & (input a falling edge signal at PA0) then generate an IRQ. Note: If PUH0, WUE and EIS are set as `1', then PA0 is defined as IRQ input pin. Figure 5-9 The Scheme of Wake_Up Register Note3: The IRQ must execute at normal mode. If an IRQ is occurred at sleep model, then the IRQ routine will be performed until this chip has woken by external wake up signal. Other wake methods include (1) power on reset, (2) external reset and (3) WDT overflow (if enabled), the foregoing cases mean the IRQ ought to be abolished.
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The Interrupt Mask register and Interrupt Flag register are used to control IRQ handling. TM58P20 supports timer0 and external interrupt but nest-interrupt is not allowed. The schemes of the interrupt mask register and the interrupt flag register are shown in Fig 5-10 and 5-11, respectively. Bit Symbol Description Global enable bit: The bit has higher priority than EXINTM and TMR0M. 1: enable 0: disable By the way, the RETI instruction will set INTM as `1'. Unimplemented External Interrupt enable: 1:Enable Interrupt 0: Disable Interrupt Unimplemented TMR0 Interrupt enable: 1:Enable Interrupt 0: Disable Interrupt Figure 5-10 Interrupt Mask register Description Unimplemented External interrupt flag: 1: the External interrupt be requested by the external interface (Port A0) (Note4) Unimplemented TMR0 interrupt flag: 1: TheTMR0 counter overflow generates an interrupt request. Figure 5-11 Interrupt Flag register
7
INTM
6~3 2 1 0
---EXINTM ---TMR0M
Bit 7~3 2 1 0
Symbol ---EXINTF ---TMR0F
Note 4: Both interrupt flags are set by hardware, software can only clear flags. It is useless that attempt writing `1' to flag.
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The debounce time is the interval that must pass before a second pressing of a key is accepted. User can set this interval with the delay routine (See Example 1). Key bounce interrup ;---------------------------------------btmss irqf,2 ;; if external IRQ? lgoto int_end int_nt1 ;; filter out key begin bounce btmsc ra,0 lgoto int_nt1 int_loop1 ;; filter out key end bounce call delay ;; worse case 30ms btmss ra,0 lgoto int_loop1 call delay_routine ;; such as 30ms btmss ra,0 lgoto int_loop1 ;------------------------------------bcm irqf,2 int_end reti Example 1 Key_Debounce
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6. Functional Description
6.1 TMR0 and Watchdog timer Fig. 6-1 shows the block diagram of the TMR0/WDT prescaler. As shown in the figure, the prescaler register can be a pre-scaler for TMR0 or be a post-scaler for WDT.
EDGE0 Instruction Cycle RTCC
SUR0
0
1 2 To 1 MUX WDT Timer
1
0 2 to 1 MUX PSA PSA
0 2 To 1 MUX
1
8-bit prescaler Synchronize with 2 internal cycles ( T2 and T4 ) 8 bit
8 To 1 MUX PS2~PS0 TMR0 Counter 1 8 bit PSA Data bus WDT time-out 2 To 1 MUX 0
Figure 6-1 Block Diagram of the TMR0/WDT Prescaler
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The TMR0 is an 8-bit timer/counter. The clock source of TMR0 can come from the instruction clock or the external clock. A. B. To select the instruction clock, the SUR0 bit of the select register should be clear. When no prescaler is used, TMR0 will increase by 1 at every instruction cycle. To select the external clock, the SUR0 bit of the select register should be set. In this mode, TMR0 relies on the EDGE0 bit to determine that TMR0 is increased by 1 at every falling or rising edge. When an external clock is used for TMR0, a problem must be noted that the external clock synchronizes with internal clock. TM58P20 synchronizes external clock by sampling internal clock at T2 and T4. If external pulse is smaller than 2 internal cycles, the pulse maybe ignored. Therefore, the external clock must keep stable state (high or low) for at least 2 internal cycles.
The WDT counter is an 8-bit binary counter. The clock source of WDT is provided by an independent on-chip RC oscillator that does not need any external clock. Therefore, the WDT will keep counting even if the chip has slept already. A WDT time-out period which is typically 20ms, it will restart system and set theTO bit (bit4 of status register) as "0". The WDT time-out period vary with temperature, power voltage and process. This period can be improved via the prescaler. The maximum division ratio can up to 1:128 by setting PS2~PS0 as "111". The prescaler can be assigned to either the TMR0 or the WDT via the PSA bit. Note that either WDT or TMR0 can employ the prescaler simultaneously. The following Example(2-3) must be executed when changing PSA form TMR0 to the WDT and form WDT to the TMR0 respectively. These examples can avoid an unintended time-out reset. Clrwdt Clrm Movla Select Clrwdt Movla Select Clrwdt ; clear prescaler & WDT Movla B'00xx0xxx Select ; set prescaler to TMR0 with ; new rate
TMR0; clear prescaler & TMR0 B'00xx1111
B'00xx1xxx; set prescaler to desired ; WDT rate Example 3 Changing prescaler form WDT to TMR0
Example 2 Changing prescaler form TMR0 to WDT
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When the prescaler is assigned to WDT, "CLRWDT" and "SLEEP" instruction will clear the prescaler and the WDT. When the prescaler is assigned to TMR0, the prescaler will be cleared by any instruction that writes to TMR0. 6.2 Reset TM58P20 may be reset by one of the following conditions: (1) Power-on (2) Power-down (circuit protection), refer to electrical character characteristic. (3) RESETB/VPP pin input a negative pulse (4) WDT timer out reset (if enabled).
Power On Power Down (Low Voltage Detector) RESETB/VPP Pin
Power
Oscillator (RC or Crystal)
Synchronize by ripple counter
Delay for Setup Time
WDTE
Reset
WDT
WDT overflow On-chip RC oscillator
Figure 6-2 Scheme of the Reset Controller As shown in the figure 6-2, four reset conditions are listed. The power-down event will cause TM58P20 to reset which the voltage ranges is according to the bit6~bit5 in the configuration word. This condition is used to protect chip in deficient power environment. The voltage ranges of power-down are defined in electrical characteristics. Furthermore, the ranges may be influenced by process and temperature variations. In general, we call the first two reset-cases as cold reset. The cold reset time may be too short for slow crystals and RC oscillators that require much longer than setup time (note) to oscillate. In order to insure the system is correct, the events should be synchronized with system clock.
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Note: the setup time is approximately 20ms that will affect due to power voltage, process and temperature variations. The last two cases are called warm reset. The different reset events will affect registers and ram. The TO and PD bits can be used to determine the type of reset. These relation are listed in figure 6-3 Address N/A N/A N/A 00h 01h 02h 03h 04h 05h 06h 07h 20h 21h 22h Name Accumulator IODIR Select IAR TMR0 PC STATUS BSR PORTA PORTB PORTC WAKE_UP IRQM IRQF General Purpose RAM Cold Reset xxxx xxxx 1111 1111 --11 1111 ---- ---xxxx xxxx 111 1111 1111 0001 1xxx -xxx xxxx 0000 xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 Xxxx xxxx 6-3 RESET CONDITIONS X: unknown; P: previous data ; ?: value depends on condition ; -:unimplemented, read as "0"
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Warm Reset pppp pppp 1111 1111 --11 1111 ---- ---pppp pppp 111 1111 1111 000? ?ppp 1 -ppp pppp 0000 pppp pppp pppp pppp pppp 0000 0000 0000 0000 2 0000 0000 Pppp pppp
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7. Instruction Set
Mnemonic Operands ADDAM M, m ADDAM M, a ANDAM M, m ANDAM M, a ANDLA I BCM M, b0 BCM M, b1 BCM M, b2 BCM M, b3 BCM M, b4 BCM M, b5 BCM M, b6 BCM M, b7 BSM M, b0 BSM M, b1 BSM M, b2 BSM M, b3 BSM M, b4 BSM M, b5 BSM M, b6 BSM M, b7 BTMSC M, b0 BTMSC M, b1 BTMSC M, b2 BTMSC M, b3 BTMSC M, b4 BTMSC M, b5 Instruction Code (Advance) (M)+(acc) / (M) (M)+(acc) / (M)D (acc) / (M)D (acc) / Literal D (acc) / (acc) (M) (acc) (acc) Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Status OP-code Affected C, DC, Z 10 0101 1MMM MMMM C, DC, Z 10 0101 0MMM MMMM Z Z Z None None None None None None None None None None None None None None None None None None None None None None 10 0100 1MMM MMMM 10 0100 0MMM MMMM 11 1001 iiii iiii 00 1100 0MMM MMMM 00 1100 1MMM MMMM 00 1101 0MMM MMMM 00 1101 1MMM MMMM 00 1110 0MMM MMMM 00 1110 1MMM MMMM 00 1111 0MMM MMMM 00 1111 1MMM MMMM 00 1000 0MMM MMMM 00 1000 1MMM MMMM 00 1001 0MMM MMMM 00 1001 1MMM MMMM 00 1010 0MMM MMMM 00 1010 1MMM MMMM 00 1011 0MMM MMMM 00 1011 1MMM MMMM 00 0100 0MMM MMMM 00 0100 1MMM MMMM 00 0101 0MMM MMMM 00 0101 1MMM MMMM 00 0110 0MMM MMMM 00 0110 1MMM MMMM
Clear bit0 of (M) Clear bit1 of (M) Clear bit2 of (M) Clear bit3 of (M) Clear bit4 of (M) Clear bit5 of (M) Clear bit6 of (M) Clear bit7 of (M) Set bit0 of (M) Set bit1 of (M) Set bit2 of (M) Set bit3 of (M) Set bit4 of (M) Set bit5 of (M) Set bit6 of (M) Set bit7 of (M)
If bit0 of (M) = 0, skip next instruction 1 + (skip) If bit1 of (M) = 0, skip next instruction 1 + (skip) If bit2 of (M) = 0, skip next instruction 1 + (skip) If bit3 of (M) = 0, skip next instruction 1 + (skip) If bit4 of (M) = 0, skip next instruction 1 + (skip) If bit5 of (M) = 0, skip next instruction 1 + (skip)
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TM58P20
BTMSC M, b6 BTMSC M, b7 BTMSS M, b0 BTMSS M, b1 BTMSS M, b2 BTMSS M, b3 BTMSS M, b4 BTMSS M, b5 BTMSS M, b6 BTMSS M, b7 CALL I CLRA CLRM M CLRWDT COMM M, m COMM M, a DECM M, m DECM M, a DECMSZ M, m DECMSZ M, a GOTO I INCM M, m INCM M, a INCMSZ M, m INCMSZ M, a IODIR M IORAM M, m IORAM M, a If bit6 of (M) = 0, skip next instruction 1 + (skip) If bit7 of (M) = 0, skip next instruction 1 + (skip) If bit0 of (M) = 1, skip next instruction 1 + (skip) If bit1 of (M) = 1, skip next instruction 1 + (skip) If bit2 of (M) = 1, skip next instruction 1 + (skip) If bit3 of (M) = 1, skip next instruction 1 + (skip) If bit4 of (M) = 1, skip next instruction 1 + (skip) If bit5 of (M) = 1, skip next instruction 1 + (skip) If bit6 of (M) = 1, skip next instruction 1 + (skip) If bit7 of (M) = 1, skip next instruction 1 + (skip) Call subroutine Clear accumulator Clear memory M Clear watch-dog register ~(M) / ~(M) / (M) (acc) 2 1 1 1 1 1 1 1 1 + (skip) 1 + (skip) 2 1 1 1 + (skip) 1 + (skip) 1 1 1 23 None None None None None None None None None None None Z Z TO, PO Z Z Z Z None None None Z Z None None None Z Z 00 0111 0MMM MMMM 00 0111 1MMM MMMM 00 0000 0MMM MMMM 00 0000 1MMM MMMM 00 0001 0MMM MMMM 00 0001 1MMM MMMM 00 0010 0MMM MMMM 00 0010 1MMM MMMM 00 0011 0MMM MMMM 00 0011 1MMM MMMM 11 0110 iiii iiii 10 0001 0000 0000 10 0001 1MMM MMMM 10 0000 0000 0001 10 0010 1MMM MMMM 10 0010 0MMM MMMM 10 0110 1MMM MMMM 10 0110 0MMM MMMM 10 0111 1MMM MMMM 10 0111 0MMM MMMM 11 101i iiii iiii 10 1000 1MMM MMMM 10 1000 0MMM MMMM 10 1001 1MMM MMMM 10 1001 0MMM MMMM 10 0000 0000 0MMM 10 1111 1MMM MMMM 10 1111 0MMM MMMM
Decrement M to M (M) - 1 / (M) - 1 / (M) - 1 / (acc)
(M), skip if (M) = 0 (acc), skip if (M) = 0 Goto branch
(M) + 1 / (M) + 1 / (M) + 1 / (M) + 1 /
(M) (acc)
(M), skip if (M) = 0 (acc), skip if (M) = 0
Set i/o direction (M) ior (acc) / (M) ior (acc) / (M) (acc)
tenx technology, inc.
Rev1.2 2004/3/5
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TM58P20
IORLA l LCALL I LGOTO I MOVAM m MOVLA l MOVM M, m MOVM M, a NOP RET RETI RETLA l RLM M, m RLM M, a RRM M, m RRM M, a SELECT SLEEP SUBAM M, m SUBAM M, a SWAPM M, m SWAPM M, a XORAM M, m XORAM M, a XORLA l Literal ior (acc) / (acc) 1 2 2 1 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 Z None None None None Z Z None None None None C C C C None TO, PO 11 0011 iiii iiii 01 0iii iiii iiii 01 1iii iiii iiii 10 0000 1MMM MMMM 11 0001 iiii iiii 10 0011 1MMM MMMM 10 0011 0MMM MMMM 10 0000 0000 0000 11 1111 0111 1111 11 1111 1111 1111 11 1100 iiii iiii 10 1100 1MMM MMMM 10 1100 0MMM MMMM 10 1110 1MMM MMMM 10 1110 0MMM MMMM 10 0000 0000 0010 10 0000 0000 0011
Call subroutine. However, LCALL can addressing 2K address Go branch to any address Move data form acc to memory Move literal to accumulator (M) / (M) / (M) (acc)
No operation Return Return and enable INTM Return and move literal to accumulator Rotate left from m to itself Rotate left from m to acc Rotate right from m to itself Rotate right from m to acc Set select register Enter sleep (saving) mode (M)-(acc) / (M) -(acc) / (M) (acc)
C, DC, Z 10 1010 1MMM MMMM C, DC, Z 10 1010 0MMM MMMM None None Z Z Z 10 1101 1MMM MMMM 10 1101 0MMM MMMM 10 1011 1MMM MMMM 10 1011 0MMM MMMM 11 1000 iiii iiii
Swap data from m to itself Swap data from m to acc (M) xor (acc) / (M) xor (acc) / Literal xor (acc) / (M) (acc) (acc)
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tenx technology, inc.
Rev1.2 2004/3/5
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TM58P20
8. Electrical Characteristics
8.1 Absolute Maximum Ratings Supply Voltage .... Vss-0.3V to Vss+5.5V Storge Temperature ....... -50J Input Voltage ...... Vss-0.3V to VDD+0.3V Operating Temperature... 0J 8.2 DC Characteristics
Symbol VDD Parameter VDD Operating Voltage --5V VDVT Detect Voltage 3V VIH VIL IDD1 IIL IOH Input HighVoltage Input Low Voltage Standby Current Input Leakage Current I/O Port Driving Current 5V 5V 5V 5V Low Voltage Detector (Idd = 3uA) Config bit6.bit5=00 Low Voltage Detector (Idd = 1.5uA) Config bit6.bit5=10 I/O Port I/O Port LVD disable, WDT disable LVD disable, WDT enable Vin=VDD, VSS Voh=4.5V Voh=4V Voh=3.5V Vol=0.5V IOL I/O Port Sink Current 5V Vol=01V Vol=1.5V 1 10 1 9 17 23 20 35 50 mA 2 Test Conditions Conditions 2.2 4 5.5 V V Min. Typ. Max. Unit
to 125J to 70J
2 VDD 0.8
V V V uA uA
5V
mA
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tenx technology, inc.
Rev1.2 2004/3/5
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TM58P20
8.3 AC Characteristics
Test Conditions Symbol fsys1 fsys2 fsys3 fsys4 Twdt Trht Parameter
System Clock System Clock System Clock System Clock Watchdog Timer Reset Hold Time
VDD
5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V
Conditions
LP Crystal mode NT Crystal mode HS Crystal mode RC mode
Min
32 32 0.2 0.2 10
Typ
Max
200 200 10 10 20 6 6
Unit
Khz Mhz Mhz Mhz mS mS
20 30 20 30
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tenx technology, inc.
Rev1.2 2004/3/5

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